IT983932B - Sistema di indirizzamento perfe zionato particolarmente per me morie ad accesso casuale rea lizzate a circuito integrato - Google Patents

Sistema di indirizzamento perfe zionato particolarmente per me morie ad accesso casuale rea lizzate a circuito integrato

Info

Publication number
IT983932B
IT983932B IT23099/73A IT2309973A IT983932B IT 983932 B IT983932 B IT 983932B IT 23099/73 A IT23099/73 A IT 23099/73A IT 2309973 A IT2309973 A IT 2309973A IT 983932 B IT983932 B IT 983932B
Authority
IT
Italy
Prior art keywords
morie
perfect
integrated circuit
random access
addressing system
Prior art date
Application number
IT23099/73A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT983932B publication Critical patent/IT983932B/it

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
IT23099/73A 1972-06-30 1973-04-17 Sistema di indirizzamento perfe zionato particolarmente per me morie ad accesso casuale rea lizzate a circuito integrato IT983932B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00267805A US3810124A (en) 1972-06-30 1972-06-30 Memory accessing system

Publications (1)

Publication Number Publication Date
IT983932B true IT983932B (it) 1974-11-11

Family

ID=23020194

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23099/73A IT983932B (it) 1972-06-30 1973-04-17 Sistema di indirizzamento perfe zionato particolarmente per me morie ad accesso casuale rea lizzate a circuito integrato

Country Status (11)

Country Link
US (1) US3810124A (en])
JP (2) JPS5636513B2 (en])
CA (1) CA1028061A (en])
CH (1) CH548084A (en])
DD (1) DD104864A5 (en])
ES (1) ES415975A1 (en])
FR (1) FR2191202B1 (en])
GB (1) GB1427156A (en])
IT (1) IT983932B (en])
NL (1) NL167789B (en])
SU (1) SU654197A3 (en])

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752669B2 (en]) * 1973-11-14 1982-11-09
FR2258783B1 (en]) * 1974-01-25 1977-09-16 Valentin Camille
GB1502270A (en) * 1974-10-30 1978-03-01 Hitachi Ltd Word line driver circuit in memory circuit
JPS51147224A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Semiconductor memory
US4025908A (en) * 1975-06-24 1977-05-24 International Business Machines Corporation Dynamic array with clamped bootstrap static input/output circuitry
US4086662A (en) * 1975-11-07 1978-04-25 Hitachi, Ltd. Memory system with read/write control lines
JPS5827440Y2 (ja) * 1975-12-31 1983-06-14 富士通株式会社 ハンドウタイキオクカイロ
JPS5922316B2 (ja) * 1976-02-24 1984-05-25 株式会社東芝 ダイナミツクメモリ装置
US4074237A (en) * 1976-03-08 1978-02-14 International Business Machines Corporation Word line clamping circuit and decoder
JPS52155928A (en) * 1976-06-21 1977-12-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
US4188671A (en) * 1977-01-24 1980-02-12 Bell Telephone Laboratories, Incorporated Switched-capacitor memory
JPS544086A (en) * 1977-06-10 1979-01-12 Fujitsu Ltd Memory circuit unit
JPS55150189A (en) * 1979-05-10 1980-11-21 Nec Corp Memory circuit
JPS5847796B2 (ja) * 1979-05-26 1983-10-25 富士通株式会社 半導体メモリ装置
JPS5619585A (en) * 1979-07-26 1981-02-24 Toshiba Corp Semiconductor memory unit
US4357687A (en) * 1980-12-11 1982-11-02 Fairchild Camera And Instr. Corp. Adaptive word line pull down
JPS57212690A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Dynamic mos memory device
JPS58153294A (ja) * 1982-03-04 1983-09-12 Mitsubishi Electric Corp 半導体記憶装置
JPS5948890A (ja) * 1982-09-10 1984-03-21 Nec Corp メモリ回路
JPS5960794A (ja) * 1982-09-29 1984-04-06 Fujitsu Ltd ダイナミツク型半導体記憶装置
JPS59116985A (ja) * 1982-11-29 1984-07-06 Fujitsu Ltd 半導体記憶装置
JPS6168865U (en]) * 1984-10-09 1986-05-12
JPH07105140B2 (ja) * 1988-12-16 1995-11-13 日本電気株式会社 半導体メモリ
EP0793176B1 (en) * 1996-03-01 1999-06-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of preventing malfunction due to disconnection of word select line
EP0953983A3 (en) * 1996-03-01 2005-10-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with clamping circuit for preventing malfunction
DE19823956A1 (de) * 1998-05-28 1999-12-02 Siemens Ag Anordnung zur Übersprechdämpfung in Wortleitungen von DRAM-Schaltungen
US20070165479A1 (en) * 2006-01-17 2007-07-19 Norbert Rehm Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1549076A1 (de) * 1967-12-22 1971-01-21 Standard Elek K Lorenz Ag Assoziativer Speicher
US3699537A (en) * 1969-05-16 1972-10-17 Shell Oil Co Single-rail mosfet memory with capacitive storage
US3708788A (en) * 1971-11-11 1973-01-02 Ibm Associative memory cell driver and sense amplifier circuit

Also Published As

Publication number Publication date
CH548084A (de) 1974-04-11
FR2191202A1 (en]) 1974-02-01
DE2324300B2 (de) 1976-06-16
NL167789B (nl) 1981-08-17
JPS5698786A (en) 1981-08-08
NL7308695A (en]) 1974-01-02
CA1028061A (en) 1978-03-14
JPS5636513B2 (en]) 1981-08-25
DD104864A5 (en]) 1974-03-20
ES415975A1 (es) 1976-05-16
GB1427156A (en) 1976-03-10
JPS5733629B2 (en]) 1982-07-17
US3810124A (en) 1974-05-07
FR2191202B1 (en]) 1976-05-28
DE2324300A1 (de) 1974-01-17
SU654197A3 (ru) 1979-03-25
JPS4945649A (en]) 1974-05-01

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